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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
FIGURE 1-1:
PSV and Table
Data Access
Control Block
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 BLOCK DIAGRAM
Y Data Bus
Interrupt
Controller
X Data Bus
PORTA
8
16
16
16
16
23
Data Latch
Data Latch
23
PCU PCH PCL
Program Counter
X RAM
Y RAM
PORTB
23
Stack
Control
Logic
Loop
Control
Logic
Address
Latch
16
Address
Latch
16
16
Remappable
Address Latch
Address Generator Units
Pins
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
Instruction Reg
DSP Engine
16
16 x 16
16
16
OSC2/CLKO
OSC1/CLKI
Timing
Generation
Power-up
Timer
Divide Support
W Register Array
16
Oscillator
FRC/LPRC
Oscillators
Start-up Timer
Power-on
Precision
Band Gap
Reference
Voltage
Regulator
V CAP
Reset
Watchdog
Timer
Brown-out
Reset
V DD , V SS
MCLR
16-bit ALU
16
CTMU
External
Interrupts
1-3
Comparators
1-3
Timers
1-3
SPI1
UART1
IC1-IC3
ADC1
CNx
OC/
PWM1-2
I2C1
RTCC
PWM
6 Ch
Note:
Not all pins or features are implemented on all device pinout configurations. See “ Pin Diagrams ” for the specific pins
and features present on each device.
DS70652C-page 16
Preliminary
? 2011 Microchip Technology Inc.
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